january 2011 ? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7wz07 ? rev. 1.0.6 nc7wz07 ? tinylogic ? uhs dual buffer (open drain outputs) nc7wz07 tinylogic ? uhs dual buffer (open drain outputs) features ? ultra-high speed: t pzl 2.3ns (typical) ? high i ol output drive: 24ma at 3v v cc ? broad v cc operating range: 1.65v to 5.50v ? power down high impedance inputs/outputs ? over-voltage tolerance input s facilitate 5v to 3v translation ? proprietary noise/emi reduction circuitry ? ultra-small micropak? packages description the nc7wz07 is a dual buffer with open drain outputs from fairchild?s ultra-high speed (uhs) series of tinylogic?. the device is fabricated with advanced cmos technology to achieve ultra-high speed with high output drive while mainta ining low static power dissipation over a broad v cc operating range. the device is specified to oper ate over a very broad v cc operating range. the device is specified to operate over the 1.65v to 5.5v v cc range. the inputs and outputs are high impedance when v cc is 0v. inputs tolerate voltages up to 7v independent of v cc operating voltage. ordering information part number top mark package packing method nc7wz07p6x z07 6-lead sc70, eiaj sc 88 1.25mm wide 3000 units on tape & reel nc7wz07l6x d3 6-lead micropak?, 1.00mm wide 5000 units on tape & reel nc7wz07fhx d3 6-lead, micropak2?, 1x1mm body, .35mm pitch 5000 units on tape & reel
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7wz07 ? rev. 1.0.6 2 nc7wz07 ? tinylogic ? uhs dual buffer (open drain outputs) connection diagrams ieee/iec figure 1. logic symbol pin configurations figure 2. sc70 (top view) figure 3. micropak? (top through view) figure 4. pin 1 orientation notes: 1. aaa represents product code top mark ( see ordering information ). 2. orientation of top mark determines pin one location. 3. reading the top mark left to right, pin one is the lower left pin. pin definitions pin # sc70 pin # micropak? name description 1 1 a 1 input 2 2 gnd ground 3 3 a 2 input 4 4 y 2 output 5 5 v cc supply voltage 6 6 y 1 output function table y= a inputs output a y l l h h* h = high logic level l = low logic level h* = high impedance output state, open drain
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7wz07 ? rev. 1.0.6 3 nc7wz07 ? tinylogic ? uhs dual buffer (open drain outputs) absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 7.0 v v in dc input voltage -0.5 7.0 v v out dc output voltage -0.5 7.0 v i ik dc input diode current v in < -0.5v -50 ma i ok dc output diode current v out < -0.5v -50 ma i out dc output current 50 ma i cc or i gnd dc v cc or ground current 100 ma t stg storage temperature range -65 +150 c t j junction temperature under bias +150 c t l junction lead temperature (sol dering, 10 seconds) +260 c p d power dissipation at +85c sc70-6 180 mw micropak?-6 130 micropak2?-6 120 esd human body model, jedec:jesd22-a114 4000 v charge device model, jedec:jesd22-c101 2000 recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc supply voltage oper ating 1.65 5.50 v supply voltage data re tention 1.5 5.5 v in input voltage 0 5.5 v v out output voltage 0 5.5 v t r , t f input rise and fall times v cc at 1.8v, 0.15v, 2.5v 0.2v 0 20 ns/v v cc at 3.3v 0.3v 0 10 v cc at 5.0v 0.5v 0 5 t a operating temperat ure -40 +85 c ? ja thermal resistance sc70-6 425 c/w micropak?-6 500 micropak2?-6 560 note: 4. unused inputs must be held high or low. they may not float.
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7wz07 ? rev. 1.0.6 4 nc7wz07 ? tinylogic ? uhs dual buffer (open drain outputs) dc electrical characteristics symbol parameter v cc conditions t a =+25c t a =-40 to +85c units min. typ. max. min. max. v ih high level input voltage 1.65 to 1.95 0.75v cc 0.75v cc v 2.30 to 5.50 0.70v cc 0.70v cc v il low level input voltage 1.65 to 1.95 0.25v cc 0.25v cc v 2.30 to 5.50 0.30v cc 0.30v cc i lkg high level output leakage current 1.65 to 5.50 v in =v ih , v out =v cc or gnd 5 10 a v ol low level output voltage 1.65 v in =v il , i ol =100a 0.00 0.10 0.00 v 1.80 0.00 0.10 0.10 2.30 0.00 0.10 0.10 3.00 0.00 0.10 0.10 4.50 0.00 0.10 0.10 1.65 i ol =4ma 0.80 0.24 0.24 2.30 i ol =8ma 0.10 0.30 0.30 3.00 i ol =16ma 0.16 0.40 0.40 3.00 i ol =24ma 0.24 0.55 0.55 4.50 i ol =32ma 0.25 0.55 0.55 i in input leakage current 0 to 5.5 0 ?? v in ?? 5.5v 0.1 1.0 a i off power off leakage current 0 v in or v out =5.5v 1 10 a i cc quiescent supply current 1.65 to 5.50 v in =5.5v, gnd 1 10 a
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7wz07 ? rev. 1.0.6 5 nc7wz07 ? tinylogic ? uhs dual buffer (open drain outputs) ac electrical characteristics symbol parameter v cc conditions t a =+25c t a =-40 to +85c units figure min. typ. max. min. max. t pzl , t plz propagation delay 1.65 c l =50pf, ru=500 ?? rd=500 ?? v i =2 x v cc 1.8 6.6 11.5 1.8 12.6 ns figure 5 figure 6 1.80 1.8 5.5 9.5 1.8 10.5 2.50 0.20 1.2 3.7 5.8 1.2 6.4 3.30 0.30 0.8 2.9 4.4 0.8 4.8 5.00 0.50 0.5 2.3 3.5 0.5 3.9 1.65 c l =50pf, ru=500 ?? rd=500 ?? v i =2 x v cc 1.8 5.5 11.5 1.8 12.6 1.80 1.8 4.3 9.5 1.8 10.5 2.50 0.20 1.2 2.8 5.8 1.2 6.4 3.30 0.30 0.8 2.1 4.4 0.8 4.8 5.00 0.50 0.5 1.4 3.5 0.5 3.9 c in input capacitance 0 2.5 pf c out output capacitance 0 4.0 c pd power dissipation capacitance (5) 3.30 3 pf figure 7 5.00 4 note: 5. c pd is defined as the value of the internal equivalent capacitance which is deriv ed from dynamic operating current consumption (i ccd ) at no output loading and operat ing at 50% duty cycle. c pd is related to i ccd dynamic operating current by the expression: i ccd =(c pd )(v cc )(f in )+(i cc static). notes: 6. c l includes load and stray capacitance. 7. input prr = 1.0mhz, t w = 500ns. figure 5. ac test circuit figure 6. ac waveforms note: 8. input=ac waveform; t r =t f =1.8ns. 9. prr=variable; duty cycle=50%. figure 7. i ccd test circuit
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7wz07 ? rev. 1.0.6 6 nc7wz07 ? tinylogic ? uhs dual buffer (open drain outputs) physical dimensions detail a scale: 60x b 1.90 2.00 0.20 0.50 min 1.00 0.80 1.10 0.80 0.10 c 0.25 0.10 0.46 0.26 0.20 gage plane (r0.10) 30 0 seating plane c 0.10 0.00 notes: unless otherwise specified a) this package conforms to eiaj sc-88, 1996. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. d) drawing filename: mkt-maa06arev6 2.100.30 0.10 ab 0.65 1.30 (0.25) 0.30 0.15 1 1.25 0.10 3 1.30 0.40 min see detail a land pattern recommendation 6 a 4 c 0.65 l symm pin one figure 8. 6-lead, sc70, eiaj sc88, 1.25mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf . package designator tape section cavity number cavity status cover type status p6x leader (start end) 125 (typical) empty sealed carrier 3000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7wz07 ? rev. 1.0.6 7 nc7wz07 ? tinylogic ? uhs dual buffer (open drain outputs) physical dimensions 2. dimensions are in millimeters 1. conforms to jedec st andard m0-252 va riation uaad 4. filename and revision: mac06arev4 notes: 3. drawing conforms to asme y14.5m-1994 top view recommened land pattern bottom view 1.45 1.00 a b 0.05 c 0.05 c 2x 2x 0.55max 0.05 c (0.49) (1) (0.75) (0.52) (0.30) 6x 1x 6x pin 1 detail a 0.075 x 45 chamfer 0.25 0.15 0.35 0.25 0.40 0.30 0.5 (0.05) 1.0 5x detail a pin 1 terminal 0.40 0.30 0.45 0.35 0.10 0.00 0.10 cba 0.05 c c 0.05 c 0.05 0.00 5x 5x 6x (0.13) 4x 6x pin 1 identifier (0.254) 5. pin one identifier is 2x length of any 5 other line in the mark code layout. figure 9. 6-lead, micropak?, 1.0mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l6x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7wz07 ? rev. 1.0.6 8 nc7wz07 ? tinylogic ? uhs dual buffer (open drain outputs) physical dimensions 1.00 b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994 notes: a. complies to jedec mo-252 standard 0.05 c a b 0.55max 0.05 c c 0.35 0.09 0.19 123 0.35 0.25 5x 6x detail a 0.60 (0.08) 4x (0.05) 6x 0.40 0.30 0.075x45 chamfer 5x 0.40 0.35 1x 0.45 6x 0.19 top view bottom view 0.66 0.10 cba .05 c 0.89 pin 1 0.05 c 2x 2x 1.00 d. landpattern recommendation is based on fsc e. drawing filename and revision: mgf06arev3 0.52 0.73 0.57 0.20 6x 1x 5x recommended land pattern for space constrained pcb detail a pin 1 lead scale: 2x alternative land pattern for universal application design. 0.90 min 250um 65 4 0.35 (0.08) 4x side view figure 10. 6-lead, micropak2?, 1x1mm body, .35mm pitch package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/packaging/micropak2_6l_tr.pdf . package designator tape section cavity number cavity status cover type status fhx leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7wz07 ? rev. 1.0.6 9 nc7wz07 ? tinylogic ? uhs dual buffer (open drain outputs)
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